/*
 * FTNANDC024 driver developed by Mychaela Falconia at CarrierComm, Inc.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License along
 * with this program; if not, write to the Free Software Foundation, Inc.,
 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
 */

#ifndef __FTNANDC024_REGS_H__
#define __FTNANDC024_REGS_H__

/* general register definitions */
#define ECC_CONTROL			0x8
#define	  ECC_ERR_MASK(x)		(1 << x)
#define	  ECC_EN(x)			(1 << (x + 8))
#define	  ECC_BASE			(1 << 16)
#define	  ECC_NO_PARITY			(1 << 17)
#define ECC_THRES_BIT_REG0		0x10
#define	ECC_THRES_BIT_REG1		0x14
#define ECC_CORRECT_BIT_REG0		0x18
#define	ECC_CORRECT_BIT_REG1		0x1C
#define	ECC_INTR_EN			0x20
#define	  ECC_INTR_SP_THRES_HIT		(1 << 3)
#define	  ECC_INTR_SP_CORRECT_FAIL	(1 << 2)
#define	  ECC_INTR_THRES_HIT		(1 << 1)
#define	  ECC_INTR_CORRECT_FAIL		(1 << 0)
#define	ECC_INTR_STATUS			0x24
#define	  ECC_ERR_SP_THRES_HIT(x)	(1 << (24 + x))
#define   ECC_ERR_SP_FAIL(x)		(1 << (16 + x))
#define	  ECC_ERR_THRES_HIT(x)		(1 << (8  + x))
#define	  ECC_ERR_FAIL(x)		(1 << x)
#define ECC_SP_THRES_BIT_REG0		0x34
#define ECC_SP_THRES_BIT_REG1		0x38
#define ECC_SP_CORRECT_BIT_REG0		0x3C
#define ECC_SP_CORRECT_BIT_REG1		0x40

#define	DEV_BUSY_STATUS_REG		0x100
#define GENERAL_SETTING_REG		0x104
#define	  CE_NUM(x)			(x << 24)
#define	  BUSY_RDY_LOC(x)		(x << 12)
#define	  CMD_STS_LOC(x)		(x << 8)
#define	  WRITE_PROTECT			(1 << 2)
#define	  DATA_INVERT			(1 << 1)
#define	  DATA_SCRAMBLER		(1 << 0)

#define MEM_ATTR_SET			0x108
#define   PG_SZ_512			(0 << 16)
#define   PG_SZ_2K			(1 << 16)
#define   PG_SZ_4K			(2 << 16)
#define   PG_SZ_8K			(3 << 16)
#define   PG_SZ_16K			(4 << 16)
#define	  ATTR_ROW_CYCLE(x)		((x - 1) << 13)
#define	  ATTR_COL_CYCLE(x)		((x - 1) << 12)
#define   ATTR_BLOCK_SIZE(x)		((x - 1) << 2)

#define	MEM_ATTR_SET2			0x10C
#define	  VALID_PAGE(x)			((x - 1) << 16)
#define   VALID_PAGE_MASK		(0x3FF << 16)

#define	FL_AC_TIMING0(x)		(0x110 + (x << 3))
#define	FL_AC_TIMING1(x)		(0x114 + (x << 3))
#define FL_AC_TIMING2(x)		(0x190 + (x << 3))
#define FL_AC_TIMING3(x)		(0x194 + (x << 3))

#define INTR_ENABLE			0x150
#define	  INTR_ENABLE_STS_CHECK_EN(x)	(1 << x)
#define INTR_STATUS			0x154
#define	  STATUS_CMD_COMPLETE(x)	(1 << (16 + x))
#define	  STATUS_FAIL(x)		(1 << x)
#define READ_STATUS_0			0x178
#define READ_STATUS_1			0x17C

#define CMDQUEUE_STATUS			0x200
#define	  CMDQUEUE_STATUS_FULL(x)	(1 << (8 + x))
#define	  CMDQUEUE_STATUS_EMPTY(x)	(1 << x)
#define	CMDQUEUE_FLUSH			0x204
#define   CMDQUEUE_FLUSH_BIT(x)		(1 << x)

#define	CMDQUEUE1(x)			(0x300 + (x << 5))
#define	CMDQUEUE2(x)			(0x304 + (x << 5))
#define	CMDQUEUE3(x)			(0x308 + (x << 5))
#define	  CMD_COUNT(x)			(x << 16)
#define	  CMD_COLUMN(x)			(x)
#define	CMDQUEUE4(x)			(0x30C + (x << 5))
#define	  CMD_COMPLETE_EN		(1 << 0)
#define	  CMD_SCALE_BY_BLOCK		(1 << 2)
#define   CMD_DMA_HANDSHAKE_EN		(1 << 4)
#define	  CMD_FLASH_TYPE(x)		((x & 0x7) << 5)
#define	  CMD_INDEX(x)			((x & 0x3FF) << 8)
#define   CMD_PROM_FLOW			(1 << 18)
#define	  CMD_SPARE_NUM(x)		(((x - 1) & 0x1F) << 19)
#define   CMD_BMC_NUM(x)		((x & 0x7) << 24)
#define   CMD_USER_MODE			(1 << 27)
#define	  CMD_BYTE_MODE			(1 << 28)
#define	  CMD_START_CE(x)		((x & 0x7) << 29)

#define	BMC_REGION_STATUS		0x400
#define	BMC_USER_ADJUST(x)		(0x404 + (x << 2))

#define AHB_SLAVEPORT_SIZE		0x508
#define   AHB_SLAVE_SPACE_512B          (1 << 0)
#define   AHB_SLAVE_SPACE_1KB           (1 << 1)
#define   AHB_SLAVE_SPACE_2KB           (1 << 2)
#define   AHB_SLAVE_SPACE_4KB           (1 << 3)
#define   AHB_SLAVE_SPACE_8KB           (1 << 4)
#define   AHB_SLAVE_SPACE_16KB          (1 << 5)
#define   AHB_SLAVE_SPACE_32KB          (1 << 6)
#define   AHB_SLAVE_SPACE_64KB          (1 << 7)
#define   AHB_RETRY_EN(ch_index)        (1 << (ch_index + 8))
#define   AHB_PREFETCH(ch_index)        (1 << (ch_index + 12))
#define   AHB_PRERETCH_LEN(x_words)     (x_words << 16)
#define   AHB_SPLIT_EN                  (1 << 25)
#define	GLOBAL_RESET			0x50C
#define DQS_DELAY			0x520
#define PROGRAMMABLE_OPCODE		0x700
#define PROGRAMMABLE_FLOW_CONTROL	0x2000
#define	SPARE_SRAM			0x1000

#define	REGBLOCK_SIZE			0x4000
#define	DATA_SRAM_OFFSET		0x20000
#define	SRAM_BUF_SIZE			16384

#define		FIXFLOW_READID			0x5F
#define		FIXFLOW_RESET			0x65
#define		FIXFLOW_READSTATUS		0x96

/* FIX_FLOW_INDEX for small page */
#define		SMALL_FIXFLOW_PAGEREAD		0x23E
#define		SMALL_FIXFLOW_READOOB		0x249
#define		SMALL_FIXFLOW_PAGEWRITE		0x26C
#define		SMALL_FIXFLOW_WRITEOOB		0x278
#define		SMALL_FIXFLOW_ERASE		0x2C1

/* FIX_FLOW_INDEX for large page */
#define		LARGE_FIXFLOW_BYTEREAD		0x8A
#define		LARGE_FIXFLOW_PAGEREAD		0x1C
#define		LARGE_FIXFLOW_PAGEWRITE		0x54
#define		LARGE_FIXFLOW_PAGEREAD_OOB	0x48
#define		LARGE_FIXFLOW_PAGEWRITE_OOB	0x26
#define		LARGE_FIXFLOW_READOOB		0x3E
#define		LARGE_FIXFLOW_WRITEOOB		0x33
#define		LARGE_FIXFLOW_ERASE		0x68

/* FIX_FLOW_INDEX for ONFI change mode */
#define		ONFI_FIXFLOW_SYNCRESET		0x21A
#define		ONFI_FIXFLOW_READPARAM		0x21D
#define		ONFI_FIXFLOW_GETFEATURE		0x22B
#define		ONFI_FIXFLOW_SETFEATURE		0x232

#endif
